PPC440EPX-SPAFFFTS datasheet(61/94 Pages) AMCC

61 / 94 page

440EPx – PPC440EPx Embedded Processor

Revision 1.26 – October 15, 2007

AMCC Proprietary

Preliminary Data Sheet

External Master Peripheral Interface

BusReq

Bus Request. Used when the PPC440EPx needs to regain

control of peripheral interface from an external master.

3.3V LVTTL

ExtAck

External Acknowledgement. Used by the PPC440EPx to indicate

that a data transfer occurred.

3.3V LVTTL

ExtReq

External Request. Used by an external master to indicate it is

prepared to transfer data.

3.3V LVTTL

ExtReset

Peripheral Reset. Used by an external master and by

synchronous peripheral slaves.

Note: The state of signals or clocks cannot be guaranteed until

the ExtReset signal has been de-asserted.

3.3V LVTTL

HoldAck

Hold Acknowledge. Used by the PPC440EPx to transfer

ownership of peripheral bus to an external master.

3.3V LVTTL

HoldReq

Hold Request. Used by an external master to request ownership

of the peripheral bus.

3.3V LVTTL

HoldPri

Hold Primary. Used by an external master to indicate the priority

of a given external master tenure.

3.3V LVTTL

w/pull-up

PerClk

Peripheral Clock. Used by an external master and by

synchronous peripheral slaves.

3.3V LVTTL

UART Peripheral Interface

The UART interface can be configured as follows:

1. One 8-pin, where n = 0

2. Two 4-pin, where n = 0 & 1

3. One 4-pin, where n = 0 and two 2-pin, where n = 1 & 2

4. Four 2-pin, where n = 0 & 1 & 2 & 3

UARTSerClk

The SerClk input provides an alternative to the internally

generated serial clock. It is used in cases where the allowable

internally generated clock rates are not satisfactory.

3.3V LVTTL

1, 4

UARTn_Rx

Receive data.

3.3V LVTTL

Rcvr

1, 4

UARTn_Tx

Transmit data.

3.3V LVTTL

UARTn_DCD

Data Carrier Detect.

3.3V LVTTL

1, 6

UARTn_DSR

Data Set Ready.

3.3V LVTTL

1, 6

UARTn_CTS

Clear To Send.

3.3V LVTTL

1, 6

UARTn_DTR

Data Terminal Ready.

3.3V LVTTL

UARTn_RTS

Request To Send.

3.3V LVTTL

UARTn_RI

Ring Indicator.

3.3V LVTTL

IIC Peripheral Interface

IIC0SClk

IIC0 Serial Clock.

I/O

3.3V LVTTL

1, 2

IIC0SData

IIC0 Serial Data.

I/O

3.3V LVTTL

1, 2

IIC1SClk

IIC1 Serial Clock.

I/O

3.3V LVTTL

IIC1SData

IIC1 Serial Data.

I/O

3.3V LVTTL

Table 8. Signal Functional Description (Sheet 5 of 9)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3k

Ω to OV

DD (EOVDD for Ethernet)

3. Must pull down (recommended value is 1k

Ω)

4. If not used, must pull up (recommended value is 3k

Ω to OV

DD (EOVDD for Ethernet)

5. If not used, must pull down (recommended value is 1k

Ω)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

PPC440EPX-SPAFFFTS Datasheet(PDF) 61 Page - Applied Micro Circuits Corporation

PPC440EPX-SPAFFFTS Datasheet(HTML) 61 Page - Applied Micro Circuits Corporation

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