TAS5802PWPR datasheet(32/106 Pages) TI2

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low switching frequency (For example, Fsw = 384 kHz) with proper LC filter (15 µH + 0.68 µF or 22 µH + 0.68

µF) is recommended. Follow these steps when using Hybrid Modulation:

1) With Hybrid Modulation, users need to input the system's PVDD value via device development application.

2) With Hybrid Modulation, Change device state from Deep Sleep Mode to Play Mode, specific sequence is

required:

1. Set device's PWM Modulation to BD or 1SPW mode via Register (Book0/Page0/Register0x02h, Bit [1:0]).

2. Set device to Hi-Z state via Register (Book0/Page0/Register0x03h, Bit [1:0]).

3. Delay 2ms.

4. Set device's PWM Modulation to Hybrid mode via Register (Book0/Page0/Register0x02h, Bit [1:0]).

5. Delay 15ms.

6. Set device to Play state via Register (Book0/Page0/Register0x03h, Bit [1:0]).

6.5 Programming and Control

6.5.1 I2C Serial Communication Bus

The device has a bidirectional serial control interface that is compatible with the Inter IC (I2C) bus protocol and

supports 100 and 400-kbps data transfer rates for random and sequential write and read operations as a target

device. Because the TAS5802 register map and DSP memory spans multiple pages and books, the user should

change from page to page or book to book before writing individual register or DSP memory. Changing from

book to book is accomplished via register 0x7F on page 0x00 of each book. Changing from page to page is

accomplished via register 0x00 on each page. This register value selects the page address, from 0 to 255.

6.5.2 Target Address

The TAS5802 device has 7 bits for the target address. The first five bits (MSBs) of the target address are factory

preset to 10101(0xAx). The next two bits of address byte are the device select bits which can be user-defined by

ADR pin in I2C Target Address Configuration.

Table 6-5. I2C Target Address Configuration

ADR/FAULT PIN

Configuration

MSBs

User Define

LSB

4.7kΩ to DVDD

R/ W

15kΩ to DVDD

R/ W

47kΩ to DVDD

R/ W

120kΩ to DVDD

R/ W

6.5.2.1 Random Write

As shown in Figure 6-12, a single-byte data-write transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of

the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address

and the read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address

byte corresponding to the internal memory address being accessed. After receiving the address byte, the device

again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the

memory address being accessed. After receiving the data byte, the device again responds with an acknowledge

bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.

Figure 6-12. Random Write Transfer

TAS5802

SLASFB7A – NOVEMBER 2024 – REVISED AUGUST 2025

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