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TAS5802PWPR Datasheet(PDF) 73 Page - Texas Instruments |
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TAS5802PWPR Datasheet(HTML) 73 Page - Texas Instruments |
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73 / 106 page  7.1.33 CHAN_FAULT Register (Offset = 70h) [Reset = 00h] CHAN_FAULT is shown in Figure 7-33 and described in Table 7-35. Return to the Summary Table. Channel fault Figure 7-33. CHAN_FAULT Register 7 6 5 4 3 2 1 0 RESERVED CH1DC CH2DC CH1OC CH2OC R-0h R-0h R-0h R-0h R-0h Table 7-35. CHAN_FAULT Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 CH1DC R 0h Channel 1 DC fault. Once there is a DC fault, the fault is latched and this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1. 2 CH2DC R 0h Channel 2 DC fault. Once there is a DC fault, the fault is latched and this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1. 1 CH1OC R 0h Channel 1 over current fault. Once there is a OC fault, the fault is latched and this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1. 0 CH2OC R 0h Channel 2 over current fault. Once there is a OC fault, the fault is latched and this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1. www.ti.com TAS5802 SLASFB7A – NOVEMBER 2024 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 73 Product Folder Links: TAS5802 |
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