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TAS5802PWPR Datasheet(PDF) 48 Page - Texas Instruments |
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TAS5802PWPR Datasheet(HTML) 48 Page - Texas Instruments |
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48 / 106 page  7.1.8 I2S_CTRL Register (Offset = 31h) [Reset = 00h] I2S_CTRL is shown in Figure 7-8 and described in Table 7-10. Return to the Summary Table. I2S control 0 Figure 7-8. I2S_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BCLK_INV RESERVED R/W-0h R/W-0h R/W-0h Table 7-10. I2S_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BCLK_INV R/W 0h BCLK Polarity This bit sets the inverted BCLK mode. In inverted BCLK mode, the DAC assumes that the LRCLK and DIN edges are aligned to the rising edge of the BCLK. Normally they are assumed to be aligned to the falling edge of the BCLK. 0: Normal BCLK mode 1: Inverted BCLK mode 4-0 RESERVED R/W 0h TAS5802 SLASFB7A – NOVEMBER 2024 – REVISED AUGUST 2025 www.ti.com 48 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: TAS5802 |
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