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TAS5802PWPR Datasheet(PDF) 63 Page - Texas Instruments |
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TAS5802PWPR Datasheet(HTML) 63 Page - Texas Instruments |
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63 / 106 page  7.1.23 ANA_CTRL Register (Offset = 53h) [Reset = 00h] ANA_CTRL is shown in Figure 7-23 and described in Table 7-25. Return to the Summary Table. Analog control Figure 7-23. ANA_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BW_CTL RESERVED PHASE_CTL R/W-0h R/W-0h R/W-0h R/W-0h Table 7-25. ANA_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 BW_CTL R/W 0h Class D Loop Bandwidth 00: 80kHz 01: 100kHz 10: 120kHz 11: 175kHz When Fsw=384kHz, 100kHz bandwidth is selected for high audio performance. With Fsw=768kHz, 175kHz bandwidth should be selected for high audio performance. 4-1 RESERVED R/W 0h 0 PHASE_CTL R/W 0h 0: Out of phase 1: In phase www.ti.com TAS5802 SLASFB7A – NOVEMBER 2024 – REVISED AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links: TAS5802 |
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