MAXQ3180-RAN+ datasheet(14/48 Pages) MAXIM

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transfers, allowing the active clock edge to signal the

start of a new transfer.

The clock rate used for the SPI interface is determined

by the bus master, since the MAXQ3180 always oper-

ates as an SPI slave device. However, the maximum

clock rate is limited by the system clock frequency of

the MAXQ3180. For proper communications operation,

the SPI clock frequency used by the master must be

less than or equal to the MAXQ3180’s clock frequency

divided by 8. For example, when the MAXQ3180 is run-

ning at 8MHz, the SPI clock frequency must be 1MHz

or less. And if the MAXQ3180 is running in LPMM Mode

(or if the crystal is still warming up), the SPI clock fre-

quency must remain at 125kHz or less for proper com-

munications operation.

In addition to limiting the overall SPI bus clock rate, the

master must also include a communications delay fol-

lowing each byte transmit/receive cycle. This delay,

which provides the MAXQ3180 with time to process the

transmitted byte, should be a minimum of 1 ADC scan

slot (time value contained in TIME_FS register, defined

as (R_ADCRATE + 1)/(system clock frequency). With

default settings and running at 8MHz, this delay time is

25μs. Reducing the system clock frequency to 1MHz

(LPMM mode) would increase this delay period by a

factor of 8μs to 200μs.

SPI Communications Protocol

All transactions between the master and the

MAXQ3180 consist of the master writing to or reading

from one of the MAXQ3180’s registers. There are sever-

al different categories of internal registers on the

MAXQ3180.

• RAM Registers. The values of these registers are

stored in the internal RAM of the MAXQ3180. Some

can be read and written by the master, while others

are read only. RAM registers are either two or four

bytes long (16 or 32 bits), although in some registers

not all the bits have defined values. Read/write regis-

ters are generally either status/flag registers (which

can be written by either the MAXQ3180 or the mas-

ter), configuration registers (which are written by the

master and read by the MAXQ3180 firmware), or

data registers (which are read only and are written

by the MAXQ3180 firmware and read by the master).

• Virtual Registers. These read-only registers are not

stored in RAM; instead, they contain values that are

calculated on the fly by the MAXQ3180 firmware

when the master reads them. These registers are

used by the master to obtain values such as phase

A, B, and C active, reactive, and apparent power;

power factor; and RMS voltage and current, which

are calculated from currently collected data on an

as-needed basis. All virtual registers are 4 bytes in

length.

• Hardware Registers. These registers control core

functions of the MAXQ3180 including the ADC and

the SPI slave bus controller. Each of these registers

(R_ACFG, R_ADCRATE, R_ADCADQ, R_SPICF, and

STATUS0 (bit 6, EXTCLK only)) has a register loca-

tion in RAM that “shadows” the value of the hardware

ter must first read from the special command register

UPD_MIR (A00h) to copy the values from the hard-

ware registers to the mirror registers in RAM, and

then the mirror register in RAM can be read. To write

to a hardware register, the master reverses the

process by writing to the mirror RAM register and

then reading from the special command register

UPD_SFR (900h) to copy the values from the mirror

registers to the hardware registers.

• Special Command Registers. These registers

(UPD_SFR and UPD_MIR) do not return meaningful

data when read but instead trigger an operation.

Reading UPD_SFR causes values to be copied from

the mirror registers to hardware, and reading

UPD_MIR causes values to be copied from the hard-

ware to mirror registers.

Every defined register on the MAXQ3180 has a 12-bit

address (from 0 to 4095). This address is used when

addressing the register for either a read or write opera-

tion. Addresses 0 to 1023 (000h to 3FFh) are used to

address RAM registers. Registers with addresses from

1024 to 4095 (400h to FFFh) are used for virtual regis-

ters and special command registers.

Each command consists of a read/write command

code, a data length (1, 2, 4, or 8 bytes), a 12-bit regis-

ter address, and the specified number of data bytes

followed optionally by a CRC. Since SPI is a full-duplex

interface, the master and slave must both transmit the

same number of bytes during the command. When a

multiple-byte register is read or written (2/4/8 byte

length), the least significant byte is read or written first

in the command.

Low-Power, Multifunction, Polyphase AFE

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