MAXQ3180-RAN+ datasheet(20/48 Pages) MAXIM

20 / 48 page

Low-Power, Multifunction, Polyphase AFE

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Table 4. RAM Register Summary (continued)

NAME

ADDRESS

(BYTE)

DESCRIPTION

R/W

DEFAULT

VALUE

(HEX)

BITS

NAME

DESCRIPTION

15:8, 6, 3,

1:0

—

Reserved. Should be set to 0.

PORF

POR flag

REV_Q

Reverse pulse 2

REV_P

Reverse pulse 1

STATUS2

0x008

Status

R/W

0x0000

WTRF

Watchdog timer flag

15:8

—

These bits are reserved and

should be set to 0

INTGN

Enable IN integrator (di/dt)

INTGC

Enable IC integrator (di/dt)

INTGB

Enable IB integrator (di/dt)

INTGA

Enable IA integrator (di/dt)

—

Reserved

INEN

Enable neutral current

CONNCT

0x00A

Connection and

Power

Calculation

Configuration

R/W

0x0000

1:0

CONNCT

[1:0]

00: P1 = VA x IA

P2 = VB x IB

P3 = VC x IC

01: P1 = VA x IA

P2 = -IB x (VA + VC)

P3 = VC x IC

1x: P1 = VA x IA

P2 = -IB x VA

P3 = VC x IC

RESERVED

12–15

—

15:12

—

These bits are reserved and

should be set to 0

11:8

MUX

Analog mux setting:

0000: V0P–VN

0001: V1P–VN

0010: V2P–VN

0011: I0P–I0N

0100: I1P–I1N

0101: I2P–I2N

0110: INP–VN

Other: Reserved

NOCONV

Disable ADC conversion for this

slot if set

SCAN_0

Analog Scan

Configuration

(Slot 0)

R/W

0x0301

6:4

PGA

PGA setting:

000: x1

001: x2

010: x4

011: x8

100: x16

101: x32

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