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NRF52820-QDAA-R Datasheet(PDF) 141 Page - Nordic Semiconductor |
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NRF52820-QDAA-R Datasheet(HTML) 141 Page - Nordic Semiconductor |
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141 / 437 page ![]() Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E D D B B B B B A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field Value ID Value Description Toggle 3 Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. E RW OUTINIT When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. Low 0 Task mode: Initial value of pin before task triggering is low High 1 Task mode: Initial value of pin before task triggering is high 6.9.5 Electrical specification 6.10 PPI — Programmable peripheral interconnect The programmable peripheral interconnect (PPI) enables peripherals to interact autonomously with each other using tasks and events independent of the CPU. The PPI allows precise synchronization between peripherals when real-time application constraints exist and eliminates the need for CPU activity to implement behavior which can be predefined using PPI. Peripheral 1 Peripheral 2 Peripheral 1 Peripheral 2 Event 1 Event 2 Event 1 Event 2 Event 3 Task 1 Task 2 Task 3 Task 1 CH[0].EEP CH[1].EEP CH[n].EEP CH[0].TEP CHEN 16MHz FORK[0].TEP 0 1 n CHG[0] 0 1 n CHG[m] 0 1 n ... Figure 44: PPI block diagram The PPI system has, in addition to the fully programmable peripheral interconnections, a set of channels where the event end point (EEP) and task end points (TEP) are fixed in hardware. These fixed channels can be individually enabled, disabled, or added to PPI channel groups (see CHG[n] registers), in the same way as ordinary PPI channels. 4463_156 v1.0 141 |
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