Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

NRF52820-QDAA-R Datasheet(PDF) 250 Page - Nordic Semiconductor

Part # NRF52820-QDAA-R
Description  nRF52820
PDF  437 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NORDIC [Nordic Semiconductor]
Direct Link  https://www.nordicsemi.com/
Logo NORDIC - Nordic Semiconductor

NRF52820-QDAA-R Datasheet(HTML) 250 Page - Nordic Semiconductor

Back Button NRF52820-QDAA-R Datasheet HTML 246Page - Nordic Semiconductor NRF52820-QDAA-R Datasheet HTML 247Page - Nordic Semiconductor NRF52820-QDAA-R Datasheet HTML 248Page - Nordic Semiconductor NRF52820-QDAA-R Datasheet HTML 249Page - Nordic Semiconductor NRF52820-QDAA-R Datasheet HTML 250Page - Nordic Semiconductor NRF52820-QDAA-R Datasheet HTML 251Page - Nordic Semiconductor NRF52820-QDAA-R Datasheet HTML 252Page - Nordic Semiconductor NRF52820-QDAA-R Datasheet HTML 253Page - Nordic Semiconductor NRF52820-QDAA-R Datasheet HTML 254Page - Nordic Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 250 / 437 page
background image
Peripherals
6.15.3 Electrical specification
6.15.3.1 SPI master interface electrical specifications
Symbol
Description
Min.
Typ.
Max.
Units
fSPI
Bit rates for SPI19
820
Mbps
tSPI,START
Time from writing TXD register to transmission started
1
µs
6.15.3.2 Serial Peripheral Interface (SPI) Master timing specifications
Symbol
Description
Min.
Typ.
Max.
Units
tSPI,CSCK
SCK period
125
ns
tSPI,RSCK,LD
SCK rise time, standard drive 21
tRF,25pF
tSPI,RSCK,HD
SCK rise time, high drive21
tHRF,25pF
tSPI,FSCK,LD
SCK fall time, standard drive21
tRF,25pF
tSPI,FSCK,HD
SCK fall time, high drive21
tHRF,25pF
tSPI,WHSCK
SCK high time21
(tCSCK/2)
– tRSCK
tSPI,WLSCK
SCK low time21
(tCSCK/2)
– tFSCK
tSPI,SUMI
MISO to CLK edge setup time
19
ns
tSPI,HMI
CLK edge to MISO hold time
18
ns
tSPI,VMO
CLK edge to MOSI valid
59
ns
tSPI,HMO
MOSI hold time after CLK edge
20
ns
tHMO
MSb
LSb
MSb
LSb
MOSI (out)
MISO (in)
CPOL=0
CPHA=0
tSUMI
tHMI
tRSCK
tFSCK
tCSCK
tWHSCK
tWLSCK
tVMO
CPOL=1
CPHA=0
CPOL=0
CPHA=1
CPOL=1
CPHA=1
Figure 98: SPI master timing diagram
19 High bit rates may require GPIOs to be set as High Drive, see GPIO chapter for more details.
20 The actual maximum data rate depends on the slave's CLK to MISO and MOSI setup and hold timings.
21 At 25 pF load, including GPIO capacitance, see GPIO electrical specification.
4463_156 v1.0
250



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com