NRF52820-QDAA-R datasheet(253/437 Pages) NORDIC

253 / 437 page

Peripherals

To ensure correct behavior, the pins used by SPIM must be configured in the GPIO peripheral as described

in GPIO configuration on page 253 before SPIM is enabled.

Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in

unpredictable behavior.

SPI master signal

SPI master pin

Direction

Output value

Comments

SCK

As specified in PSEL.SCK

on page 258

Output

Same as CONFIG.CPOL

MOSI

As specified in PSEL.MOSI

on page 259

Output

MISO

As specified in PSEL.MISO

on page 259

Input

Not applicable

Table 75: GPIO configuration

SPIM does not support automatic control of CSN. The available GPIO pins need to be used to control CSN

directly.

SPIM supports SPI modes 0 through 3. The clock polarity (CPOL) and the clock phase (CPHA) are

configured in register CONFIG on page 262.

Mode

Clock polarity

Clock phase

CPOL

CPHA

SPI_MODE0

0 (Active High)

0 (Leading)

SPI_MODE1

0 (Active High)

1 (Trailing)

SPI_MODE2

1 (Active Low)

0 (Leading)

SPI_MODE3

1 (Active Low)

1 (Trailing)

Table 76: SPI modes

6.16.3 EasyDMA

SPIM implements EasyDMA for accessing RAM without CPU involvement.

The SPIM peripheral implements the following EasyDMA channels.

Channel

Type

TXD

READER

TXD

RXD

WRITER

RXD

Table 77: SPIM EasyDMA Channels

For detailed information regarding the use of EasyDMA, see EasyDMA on page 37.

The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next

transmission immediately after having received the STARTED event.

The SPI master will automatically stop transmitting after TXD.MAXCNT bytes have been transmitted

and RXD.MAXCNT bytes have been received. If RXD.MAXCNT is larger than TXD.MAXCNT, the remaining

transmitted bytes will contain the value defined in the ORC register. If TXD.MAXCNT is larger than

RXD.MAXCNT, the superfluous received bytes will be discarded.

The ENDRX/ENDTX event indicate that EasyDMA has finished accessing respectively the RX/TX buffer in

RAM. The END event gets generated when both RX and TX are finished accessing the buffers in RAM.

4463_156 v1.0

253

NRF52820-QDAA-R Datasheet(PDF) 253 Page - Nordic Semiconductor

NRF52820-QDAA-R Datasheet(HTML) 253 Page - Nordic Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL