NRF52820-QDAA-R datasheet(264/437 Pages) NORDIC

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Peripherals

EasyDMA

RAM

SPIS

ACQUIRED

RXD.PTR

TXD.PTR

TXD+1

TXD

TXD+n

TXD+2

RXD+1

RXD

RXD+n

RXD+2

EasyDMA

MISO

MOSI

ACQUIRE

RELEASE

OVERFLOW

PSEL.MISO

PSEL.MOSI

PSEL.CSN

PSEL.SCK

Semaphore

SPI slave tranceiver

DEF

CSN

END

OVERREAD

Figure 102: SPI slave

The SPIS supports SPI modes 0 through 3. The CONFIG register allows setting CPOL and CPHA

appropriately.

Mode

Clock polarity

Clock phase

CPOL

CPHA

SPI_MODE0

0 (Active High)

0 (Trailing Edge)

SPI_MODE1

0 (Active High)

1 (Leading Edge)

SPI_MODE2

1 (Active Low)

0 (Trailing Edge)

SPI_MODE3

1 (Active Low)

1 (Leading Edge)

Table 80: SPI modes

6.17.1 Shared resources

The SPI slave shares registers and other resources with other peripherals that have the same ID as the SPI

slave. Therefore, you must disable all peripherals that have the same ID as the SPI slave before the SPI

slave can be configured and used.

Disabling a peripheral that has the same ID as the SPI slave will not reset any of the registers that are

shared with the SPI slave. It is important to configure all relevant SPI slave registers explicitly to secure that

it operates correctly.

The Instantiation table in Instantiation on page 18 shows which peripherals have the same ID as the SPI

slave.

6.17.2 EasyDMA

The SPIS implements EasyDMA for accessing RAM without CPU involvement.

The SPIS peripheral implements the following EasyDMA channels.

4463_156 v1.0

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NRF52820-QDAA-R Datasheet(PDF) 264 Page - Nordic Semiconductor

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