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NRF52820-QDAA-R Datasheet(PDF) 267 Page - Nordic Semiconductor |
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NRF52820-QDAA-R Datasheet(HTML) 267 Page - Nordic Semiconductor |
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267 / 437 page  Peripherals 6.17.4 Pin configuration The CSN, SCK, MOSI, and MISO signals associated with the SPI slave are mapped to physical pins according to the configuration specified in the PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers respectively. If the CONNECT field of any of these registers is set to Disconnected, the associated SPI slave signal will not be connected to any physical pins. The PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers and their configurations are only used as long as the SPI slave is enabled, and retained only as long as the device is in System ON mode. See POWER — Power supply on page 49 chapter for more information about power modes. When the peripheral is disabled, the pins will behave as regular GPIOs and use the configuration in their respective OUT bit field and PIN_CNF[n] register. PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO must only be configured when the SPI slave is disabled. To secure correct behavior in the SPI slave, the pins used by the SPI slave must be configured in the GPIO peripheral as described in GPIO configuration before enabling peripheral on page 267 before enabling the SPI slave. This is to secure that the pins used by the SPI slave are driven correctly if the SPI slave itself is temporarily disabled, or if the device temporarily enters System OFF. This configuration must be retained in the GPIO for the selected I/Os as long as the SPI slave is to be recognized by an external SPI master. The MISO line is set in high impedance as long as the SPI slave is not selected with CSN. Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. SPI signal SPI pin Direction Output value Comment CSN As specified in PSEL.CSN Input Not applicable SCK As specified in PSEL.SCK Input Not applicable MOSI As specified in PSEL.MOSI Input Not applicable MISO As specified in PSEL.MISO Input Not applicable Emulates that the SPI slave is not selected. Table 82: GPIO configuration before enabling peripheral 6.17.5 Registers Base address Peripheral Instance Description Configuration 0x40003000 SPIS SPIS0 SPI slave 0 0x40004000 SPIS SPIS1 SPI slave 1 Table 83: Instances Register Offset Description TASKS_ACQUIRE 0x024 Acquire SPI semaphore TASKS_RELEASE 0x028 Release SPI semaphore, enabling the SPI slave to acquire it EVENTS_END 0x104 Granted transaction completed EVENTS_ENDRX 0x110 End of RXD buffer reached EVENTS_ACQUIRED 0x128 Semaphore acquired SHORTS 0x200 Shortcuts between local events and tasks INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt SEMSTAT 0x400 Semaphore status register STATUS 0x440 Status from last transaction ENABLE 0x500 Enable SPI slave PSEL.SCK 0x508 Pin select for SCK PSEL.MISO 0x50C Pin select for MISO signal 4463_156 v1.0 267 |
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