NRF52820-QDAA-R datasheet(265/437 Pages) NORDIC

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Peripherals

Channel

Type

TXD

READER

TXD

RXD

WRITER

RXD

Table 81: SPIS EasyDMA Channels

For detailed information regarding the use of EasyDMA, see EasyDMA on page 37.

If RXD.MAXCNT is larger than TXD.MAXCNT, the remaining transmitted bytes will contain the value defined

in the ORC register.

The END event indicates that EasyDMA has finished accessing the buffer in RAM.

6.17.3 SPI slave operation

SPI slave uses two memory pointers, RXD.PTR and TXD.PTR, that point to the RXD buffer (receive buffer)

and TXD buffer (transmit buffer) respectively. Since these buffers are located in RAM, which can be

accessed by both the SPI slave and the CPU, a hardware based semaphore mechanism is implemented to

enable safe sharing.

See SPI transaction when shortcut between END and ACQUIRE is enabled on page 266.

Before the CPU can safely update the RXD.PTR and TXD.PTR pointers, it must first acquire the SPI

semaphore. The CPU can acquire the semaphore by triggering the ACQUIRE task and then receiving the

ACQUIRED event. When the CPU has updated the RXD.PTR and TXD.PTR pointers the CPU must release the

semaphore before the SPI slave will be able to acquire it. The CPU releases the semaphore by triggering

the RELEASE task. This is illustrated in SPI transaction when shortcut between END and ACQUIRE is

enabled on page 266. Triggering the RELEASE task when the semaphore is not granted to the CPU will

have no effect.

The semaphore mechanism does not, at any time, prevent the CPU from performing read or write access

to the RXD.PTR register, the TXD.PTR registers, or the RAM that these pointers are pointing to. The

semaphore is only telling when these can be updated by the CPU so that safe sharing is achieved.

The semaphore is by default assigned to the CPU after the SPI slave is enabled. No ACQUIRED event will be

generated for this initial semaphore handover. An ACQUIRED event will be generated immediately if the

ACQUIRE task is triggered while the semaphore is assigned to the CPU.

The SPI slave will try to acquire the semaphore when CSN goes low. If the SPI slave does not manage to

acquire the semaphore at this point, the transaction will be ignored. This means that all incoming data on

MOSI will be discarded, and the DEF (default) character will be clocked out on the MISO line throughout

the whole transaction. This will also be the case even if the semaphore is released by the CPU during the

transaction. In case of a race condition where the CPU and the SPI slave try to acquire the semaphore at

the same time, as illustrated in lifeline item 2 in SPI transaction when shortcut between END and ACQUIRE

is enabled on page 266, the semaphore will be granted to the CPU.

If the SPI slave acquires the semaphore, the transaction will be granted. The incoming data on MOSI will

be stored in the RXD buffer and the data in the TXD buffer will be clocked out on MISO.

When a granted transaction is completed and CSN goes high, the SPI slave will automatically release the

semaphore and generate the END event.

As long as the semaphore is available, the SPI slave can be granted multiple transactions one after the

other. If the CPU is not able to reconfigure the TXD.PTR and RXD.PTR between granted transactions, the

same TX data will be clocked out and the RX buffers will be overwritten. To prevent this from happening,

the END_ACQUIRE shortcut can be used. With this shortcut enabled, the semaphore will be handed over

to the CPU automatically after the granted transaction has completed. This enables the CPU to update the

TXPTR and RXPTR between every granted transaction.

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