NRF52820-QDAA-R datasheet(308/437 Pages) NORDIC

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Peripherals

6.22.1 EasyDMA

The TWIM implements EasyDMA for accessing RAM without CPU involvement.

The TWIM peripheral implements the EasyDMA channels found in the following table.

Channel

Type

TXD

READER

TXD

RXD

WRITER

RXD

Table 93: TWIM EasyDMA Channels

For detailed information regarding the use of EasyDMA, see EasyDMA on page 37.

The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next RX/

TX transmission immediately after having received the RXSTARTED/TXSTARTED event.

The STOPPED event indicates that EasyDMA has finished accessing the buffer in RAM.

6.22.2 Master write sequence

A TWI master write sequence is started by triggering the STARTTX task. After the STARTTX task has been

triggered, the TWI master will generate a start condition on the TWI bus, followed by clocking out the

address and the READ/WRITE bit set to 0 (WRITE=0, READ=1).

The address must match the address of the slave device that the master wants to write to. The READ/

WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK=1) generated by the slave.

After receiving the ACK bit, the TWI master will clock out the data bytes found in the transmit buffer

located in RAM at the address specified in the TXD.PTR register. Each byte clocked out from the master will

be followed by an ACK/NACK bit clocked in from the slave.

A typical TWI master write sequence is shown in the following figure. Occurrence 2 in the figure illustrates

clock stretching performed by the TWI master following a SUSPEND task.

A SUSPENDED event indicates that the SUSPEND task has taken effect. This event can be used to

synchronize the software.

The TWI master will generate a LASTTX event when it starts to transmit the last byte, this is shown in the

following figure.

ADDR

N-1

Stretch

Figure 115: TWI master writing data to a slave

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