NRF52820-QDAA-R datasheet(311/437 Pages) NORDIC

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Peripherals

ADDR

Stretch

ADDR

Figure 118: Double repeated start sequence

6.22.5 Low power

When putting the system in low power and the peripheral is not needed, lowest possible power

consumption is achieved by stopping, and then disabling the peripheral.

When the STOP task is sent, the software shall wait until the STOPPED event is received as a response

before disabling the peripheral through the ENABLE register. If the peripheral is already stopped, the STOP

task is not required.

6.22.6 Master mode pin configuration

The SCL and SDA signals associated with the TWI master are mapped to physical pins according to the

configuration specified in the PSEL.SCL and PSEL.SDA registers respectively.

The PSEL.SCL and PSEL.SDA registers and their configurations are only used as long as the TWI master is

enabled, and retained only as long as the device is in ON mode. When the peripheral is disabled, the pins

will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n]

To secure correct signal levels on the pins used by the TWI master when the system is in OFF mode, and

when the TWI master is disabled, these pins must be configured in the GPIO peripheral as described in the

following table.

Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in

unpredictable behavior.

TWI master signal

TWI master pin

Direction

Output value

Drive strength

SCL

As specified in PSEL.SCL

Input

Not applicable

S0D1

SDA

As specified in PSEL.SDA

Input

Not applicable

S0D1

Table 94: GPIO configuration before enabling peripheral

6.22.7 Registers

Base address

Peripheral

Instance

Description

Configuration

0x40003000

TWIM

TWIM0

Two-wire interface master 0

0x40004000

TWIM

TWIM1

Two-wire interface master 1

Table 95: Instances

4463_156 v1.0

311

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