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HD4046212RFS Datasheet(PDF) 76 Page - Renesas Technology Corp |
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HD4046212RFS Datasheet(HTML) 76 Page - Renesas Technology Corp |
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76 / 157 page  HD404629R Series 74 1 output: The operation is basically the same as that of timer-B’s 1 output. PWM output: The operation is basically the same as that of timer-C’s PWM output. • Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVND. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (ESR2: $027). When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL: $011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0. By selecting the input capture operation, pin R1 2/TOD is set to R12 and timer D is reset to $00. |
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