7643 datasheet(34/121 Pages) RENESAS

34 / 121 page

Rev.2.00

Aug 28, 2006

page 34 of 119

7643 Group

REJ03B0054-0200

The Framing Error Flag (FER) is set to “1” when the number of

stop bit of the received data does not correspond with the selec-

tion with the Stop Bit Length Select Bit (STB).

The Overrun Flag Flag (OER) is set to “1” if the previous data in

the low-order byte of the receive buffer register 1 (addresses

003416) is not read before the current receive operation is com-

pleted. It is also set “1” if any one of error flags is “1” for the

previous data and the current receive operation is completed. Be

sure to read UART status register to clear the error flags before

the next reception has been completed.

[UART Control Register (UCON)] 003316

The UART control register consists of eight control bits for the

UART function. This register can enable the CTS, RTS and UART

address mode.

If the Transmit Enable Bit (TEN) is set to “0” (disabled) while a

data is being transmitted, the transmitting operation will stop after

the data has been transmitted. If the Receive Enable Bit (REN) is

set to “0” (diabled) while a data is being received, the receiving

operation will stop after the data has been received.

When setting the Transmit Initialization Bit (TIN) to “1”, the TEN bit

is set to “0” and the UART status register will be set to “0316” after

the data has been transmitted. To retransmit, set the TEN to “1”

and set a data to the transmit buffer register again. The TIN bit will

be cleared to “0” one cycle later after the TIN bit has been set to

“1”.

Setting the Receive Initialization Bit (RIN) to “1” sets all of the

REN, RBF and the receive error flags (PER, FER, OER, SER) to

“0”. The RIN bit will be cleared to “0” one cycle later after the RIN

bit has been set to “1”.

_______

When CTS or RTS function is disabled, pins CTS and RTS can be

used as ordinary I/O ports, correspondingly.

[UART Transmit/Receive Buffer Registers 1, 2 (UTRB1/

UTRB2)] 003416, 003516

The transmit buffer register and the receive buffer register are lo-

cated at the same address. The transmit buffer register is

write-only and the receive buffer register is read-only. If a charac-

ter bit length is 7 bits, the MSB of received data is invalid. If a

character bit length is 7 or 8 bits, the received contents of UTRB2

are also invalid. If a character bit length is 9 bits, the received

high-order 7 bits of UTRB2 are “0”.

[UART RTS Control Register (URTS)] 003616

The delay time from the reception of the last stop bit to the asser-

_______

tion of RTS is selectable using the RTS Assertion Delay Count

_______

Select Bits. If the stop bit is detected before RTS assertion delay

_______

time has expired, the RTS pin is kept “H”. The RTS assertion de-

lay count starts after the last data reception is completed.

Setting the RIN bit to “1” resets the URTS. After setting the RIN bit

to “1”, set this URTS.

7643 Datasheet(PDF) 34 Page - Renesas Technology Corp

7643 Datasheet(HTML) 34 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL