7643 datasheet(91/121 Pages) RENESAS

91 / 121 page

Rev.2.00

Aug 28, 2006

page 91 of 119

7643 Group

REJ03B0054-0200

Software Commands (CPU Rewrite Mode)

Table 21 lists the software commands.

After setting the CPU Rewrite Mode Select Bit of the flash memory

control register to “1”, execute a software command to specify an

erase or program operation.

Each software command is explained below.

qRead Array Command (FF16)

The read array mode is entered by writing the command code

“FF16” in the first bus cycle. When an address to be read is input in

one of the bus cycles that follow, the contents of the specified ad-

dress are read out at the data bus (DB0 to DB7).

The read array mode is retained intact until another command is

written.

qRead Status Register Command (7016)

The read status register mode is entered by writing the command

code “7016” in the first bus cycle. The contents of the status regis-

ter are read out at the data bus (DB0 to DB7) by a read in the

second bus cycle.

The status register is explained in the next section.

qClear Status Register Command (5016)

This command is used to clear the bits SR4 and SR5 of the status

tion has ended in an error. To use this command, write the

command code “5016” in the first bus cycle.

qProgram Command (4016)

Program operation starts when the command code “4016” is writ-

ten in the first bus cycle. Then, if the address and data to program

are written in the 2nd bus cycle, program operation (data program-

ming and verification) will start.

Whether the write operation is completed can be confirmed by

_____

reading the status register or the RY/BY Status Flag of the flash

memory control register. When the program starts, the read status

Table 21 List of software commands (CPU rewrite mode)

tus register is read at the data bus (DB0 to DB7). The status

tion starts and is returned to “1” upon completion of the write

operation. In this case, the read status register mode remains ac-

tive until the next command is written.

____

The RY/BY Status Flag is “0” (busy) during write operation and “1”

(ready) when the write operation is completed as is the status reg-

ister bit 7.

At program end, program results can be checked by reading bit 4

(SR4) of the status register.

Fig. 81 Program flowchart

Command

Program

Clear status register

Read array

Read status register

First bus cycle

Second bus cycle

FF16

7016

5016

4016

Write

XSRD

Read

Write

Erase all blocks2016

Write

2016

Write

(Note 1)

WA (Note 2)

WD (Note 2)

Block erase

2016

Write

D016

WriteBA (Note 3)

Mode

Address

Mode

Address

Data

(DB0 to DB7)

(Note 4)

Notes 1: SRD = Status Register Data

2: WA = Write Address, WD = Write Data

3: BA = Block Address to be erased (Input the maximum address of each block.)

4: X denotes a given address in the User ROM area .

Cycle number

Data

Start

Write 4016

Status register

read

Program

completed

YES

Write address

Write data

SR4 = 0 ?

Program

error

YES

SR7 = 1 ?

RY/BY = 1 ?

Write

7643 Datasheet(PDF) 91 Page - Renesas Technology Corp

7643 Datasheet(HTML) 91 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL