7643 datasheet(5/121 Pages) RENESAS

5 / 121 page

Rev.2.00

Aug 28, 2006

page 5 of 119

7643 Group

REJ03B0054-0200

Name

Function except a port function

Function

Table 2 Pin description (2)

P60–P67

• 8-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be individually

programmed as either input or output.

• 5-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be individually

programmed as either input or output.

• 8-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be individually pro-

grammed as either input or output.

P70,

__________

P71/HOLD,

P72,

__________

P73/HLDA,

P74

__________

P80/SRDY,

P81/SCLK,

P82/SRXD,

P83/STXD,

P84/UTXD,

P85/URXD,

________

P86/CTS,

________

P87/RTS

• Serial I/O pin

Remarks

•DMAOUT pin

If externally detecting the timing of DMA execution, use the signal from this pin. It is “H” level during DMA transferring. This signal is valid in the memory expansion

and microprocessor modes.

•SYNCOUT pin

If externally detecting the timing of OP code fetch, use the signal from this pin. This signal is valid in the memory expansion and microprocessor modes.

I/O port P6

I/O port P7

• UART pin

I/O port P8

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