7643 datasheet(15/121 Pages) RENESAS

15 / 121 page

Rev.2.00

Aug 28, 2006

page 15 of 119

7643 Group

REJ03B0054-0200

Table 6 List of I/O port function

Name

Port P0

Port P1

Port P2

Input/Output

Input/Output,

individual bits

I/O format

CMOS input level

CMOS 3-state output

Non-port function

Lower address

output

Higher address

output

Data bus I/O

Related SFRs

CPU mode register A

Port control register

Ref. No.

(1)

P00/AB0–

P07/AB7

P10/AB8–

P17/AB15

P20/DB0–

P27/DB7

P60–P67

P70,

__________

P71/HOLD,

P72,

__________

P73/HLDA,

P74

__________

P80/SRDY,

P81/SCLK,

P82/SRXD,

P83/STXD,

P84/UTXD,

P85/URXD,

_______

P86/CTS,

_______

P87/RTS

(2)

CPU mode register A

Port control register

Port P2 pull-up control

CPU mode register A

CPU mode register B

Port control register

CPU mode register A

CPU mode register B

Port control register

Interrupt polarity select register

CPU mode register A

Port control register

Clock control register

Timer 123 mode register

Port control register

Control signal I/O

CMOS input level/VIHL

input level

CMOS 3-state output

Port P3

(1)

(3)

(4)

(5)

CMOS input level

CMOS 3-state output

P30/RDY–

P37/RD

P40/EDMA,

Port P4

P41/INT0,

P42/INT1,

P43,P44

Control signal I/O

External interrupt

P50/XCIN,

P51/TOUT/

XCOUT

CMOS input level

CMOS 3-state output

(6)

(7)

Timer 1, Timer 2

output pin

Sub-clock generat-

ing input pin

P52–P57

Port P5

CMOS input level

CMOS 3-state output

(8)

CMOS input level/TTL

input level

CMOS 3-state output

CMOS input level

CMOS 3-state output

CMOS input level

CMOS 3-state output

CMOS input level

CMOS 3-state output

(9)

Port control register

CPU mode register B

UART control registers

Serial I/O control register 1

Serial I/O control register 2

Port control register

Port P6

Port P7

(10)

(11)

(12)

(13)

(14)

Control signal I/O

Serial I/O I/O pin

UART I/O pin

(15)

(16)

(17)

(18)

(19)

(20)

(21)

(22)

Port P8

Notes 1: For details of the ports functions in modes other than single-chip mode, and how to use double-function ports as function I/O ports, refer to the applicable

sections.

2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.

When an input level is at an intermediate potential, a rush current will flow from VCC to VSS through the input-stage gate.

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