7643 datasheet(49/121 Pages) RENESAS

49 / 121 page

Rev.2.00

Aug 28, 2006

page 49 of 119

7643 Group

REJ03B0054-0200

USB interrupt enable register 2 (address 005516)

USBIE2

Reserved bit (Undefined at read/“0” at write)

Reserved bit (“0” at read/write)

Reserved bit (Undefined at read/“0” at write)

Reserved bit (“1” at read/write)

Reserved bit (“0” at read/write)

USB suspend/resume interrupt enable bit (INTEN15)

0: Disabled

1: Enabled

✕✕

Fig. 41 Structure of USB interrupt enable register 2

[USB Endpoint Index Register] USBINDEX

This register specifies the accessible endpoint. It serves as an in-

dex to endpoint-specific USB Endpoint x IN Control Register, USB

Endpoint x OUT Control Register, USB Endpoint x IN Max. Packet

Size Register, USB Endpoint x OUT Max. Packet Size Register,

USB Endpoint x OUT Write Count Register, and USB FIFO Mode

Selection Register (x = 0 to 2).

USB endpoint index register (address 005816)

USBINDEX

Endpoint index bit (EPINDEX) (Note)

b2b1b0

0 0 0: Endpoint 0

0 0 1: Endpoint 1

0 1 0: Endpoint 2

0 1 1: Not used

1 0 0: Not used

1 0 1: Not used

1 1 0: Not used

1 1 1: Not used

Reserved bit (“0” at read/write)

000

Note: Do not set Endpoint except Endpoint 0, 1 and 2.

Fig. 42 Structure of USB frame number registers

7643 Datasheet(PDF) 49 Page - Renesas Technology Corp