7643 datasheet(32/121 Pages) RENESAS

32 / 121 page

Rev.2.00

Aug 28, 2006

page 32 of 119

7643 Group

REJ03B0054-0200

UTXD output (P84/UTXD)

Transfer clock

Tranmit enable bit

Transmit buffer

empty flag

Transmit complete flag

Data set into UART transmit buffer register 1

Data transferring from UART transmit

buffer register 1 to Transmit shift register 1

This timing applies to the conditions:

•Character length = 8 bits

•Parity enabled

•1 stop bit

q RTS (Request-to-Send) Function

As a receiver, the UART can be configured to generate the Re-

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quest-to-Send (RTS) handshaking signal. This is enabled by

setting the RTS Function Enable Bit (bit 6 of UCON) to “1”.

When reception is enabled, that is the Receive Enable Bit is “1”,

the RTS pin goes “L” to inform a transmitter that reception is pos-

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sible. The RTS pin goes “H” at reception starting and does “L” at

receiving of the last bit.

The delay time from the reception of the last stop bit to the asser-

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tion of RTS is selectable using the RTS Assertion Delay Count

Select Bits.

BRG count source

URXD (P85/URXD)

RTS pin (P87/RTS)

Receive enable bit

Receive buffer

empty flag

Transfer clock

Transfer clock generated at falling edge

of start bit and receive started

Receive data latched

Data transferring from UART receive register 1

to Receive buffer register 1 (Note)

Note: When no RTS assertion delay, the RTS pin goes “L”.

The RTS assertion delay counts are selected by bits 4 to 7 of UART RTS control register.

This timing applies to the conditions:

•Character length = 8 bits

•Parity enabled

•1 stop bit

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Fig. 26 UART transmit timing (CTS function disbled)

When the Receive Enable Bit is set to “0” or the Receive initializa-

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tion bit is set to “1”, the RTS pin goes “H”. Even when the Receive

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Enable Bit is set to “1”, the RTS pin goes “H” if detecting an invalid

start bit.

Figure 27 shows the UART receive timing.

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Fig. 27 UART receiving timing (RTS function enabled)

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