DS72011RB120FPV datasheet(244/1196 Pages) RENESAS

244 / 1196 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 216 of 1164

REJ09B0321-0200

Bit

Bit Name

Initial

Value

R/W

Description

EWENB

R/W

External Wait Enable

This bit is used to enable or disable external wait input.

When EWENB is set to 1, external wait input is

enabled and the number of wait states per cycle can be

controlled using the external wait signal (

WAIT). In this

case wait cycles are inserted while the

WAIT signal is

low level. When EWENB is cleared to 0, the

WAIT

signal is invalid.

0: External wait disabled

1: External wait enabled

18, 17



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

WRMOD

R/W

Write Access Mode Select

This bit selects the operating mode for write access.

Clearing WRMOD to 0 selects the byte-write strobe

mode. In this mode data writes are controlled by

multiple write signals (

WR3 to WR0) that correspond to

the individual byte positions. Setting WRMOD to 1

selects the one-write strobe mode. In this mode, data

writes are controlled by multiple byte control signals

(

BC3 to BC0) that correspond to the individual byte

positions and a single write signal (

WR0 for the 8-bit

bus width channel,

WR1 for the 16-bit bus width

channel, and

WR3 for the 32-bit bus width channel)

0: Byte-write strobe mode

1: One-write strobe mode

15 to 0



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

Writing to the CSn mode register (CSMODn) must be done while CSC for the corresponding

channel is disabled (EXENB

= 0). Only channel 0 (CS0) can be enabled by setting EXENB = 1.

To enable channel 0, stop the DMAC and set EXENB to 1 between the reset release and data write

access to CS0.

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