DS72011RB120FPV datasheet(246/1196 Pages) RENESAS

246 / 1196 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 218 of 1164

REJ09B0321-0200

Bit

Bit Name

Initial

Value

R/W

Description

10 to 8

CSPRWAIT

[2:0]

111

R/W

Page Read Cycle Wait Select

These bits specify the number of wait states inserted

into the second and subsequent page read cycles. This

setting is valid when the page read access enable bit

(PRENB) is set to 1.

000: 0 wait state

111: 7 wait states

7 to 3



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

2 to 0

CSPWWAIT

[2:0]

111

R/W

Page Write Cycle Wait Select

These bits specify the number of wait states inserted

into the second and subsequent page write cycles.

This setting is valid when the page write access enable

bit (PWENB) is set to 1.

000: 0 wait state

111: 7 wait states

Notes: 1. Make sure the page read and page write cycle wait select (CSPRWAIT and

CSPWWAIT) settings are within the range defined by the read and write cycle wait

select (CSRWAIT and CSWWAIT) settings. Select each wait cycle number according

the system configuration incorporated.

2. Writing to the CSn wait control register 1 (CS1WCNTn) must be done while CSC for the

corresponding channel is disabled (EXENB

= 0). Only channel 0 (CS0) can be enabled

by setting EXENB = 1. To enable channel 0, stop the DMAC and set EXENB to 1

between the reset release and data write access to CS0.

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