DS72011RB120FPV datasheet(319/1196 Pages) RENESAS

319 / 1196 page

Section 10 Bus Monitor

Rev. 2.00 Sep. 07, 2007 Page 291 of 1164

REJ09B0321-0200

10.1.3

Bus Monitor Status Register 2 (SYCBESTS2)

SYCBESTS2 indicates the status of slave buses (external bus/peripheral bus (2)/others) regarding

whether a timeout occurred, whether an illegal address access was made, or which bus master

accessed the slave bus.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000000

—

———

————————

ETO

EER

EMST[1:0]

—

OER

—

OMST[1:0]

—

SHER

—

SHMST[1:0]

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should

always be 0.

ETO

Timeout

This bit indicates that a timeout occurred on the

external bus when the first bus error occurred.

0: Timeout not generated

1: Timeout generated

EER

Illegal Address Access

This bit indicates that an illegal address access was

made on the external bus when the first bus error

occurred.

0: Illegal address access not made

1: Illegal address access made

28 to 26



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

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