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DS72011RB120FPV Datasheet(PDF) 321 Page - Renesas Technology Corp |
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DS72011RB120FPV Datasheet(HTML) 321 Page - Renesas Technology Corp |
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321 / 1196 page ![]() Section 10 Bus Monitor Rev. 2.00 Sep. 07, 2007 Page 293 of 1164 REJ09B0321-0200 Bit Bit Name Initial Value R/W Description 4 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 SHMST [1:0] 00 R Bus Master These bits indicate the bus master that accessed peripheral bus (2) when the first bus error occurred. 00: CPU 01: DMAC (destination side) 10: Setting prohibited 11: DMAC (source side) |
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