DS72011RB120FPV datasheet(320/1196 Pages) RENESAS

320 / 1196 page

Section 10 Bus Monitor

Rev. 2.00 Sep. 07, 2007 Page 292 of 1164

REJ09B0321-0200

Bit

Bit Name

Initial

Value

R/W

Description

25, 24

EMST[1:0]

Bus Master

These bits indicate the bus master that accessed the

external bus when the first bus error occurred.

00: CPU

01: DMAC (destination side)

10: Setting prohibited

11: DMAC (source side)

23 to 14



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

OER

Illegal Address Access

These bits indicate the bus master that accessed other

buses when the first bus error occurred.

0: Illegal address access not made

1: Illegal address access made

12 to 10



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

9, 8

OMST[1:0]

R/W

Bus Master

These bits indicate the bus master that accessed other

buses when the first bus error occurred.

00: CPU

01: DMAC (destination side)

10: Setting prohibited

11: DMAC (source side)

7, 6



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

SHER

Illegal Address Access

This bit indicates that an illegal address access was

made on peripheral bus (2) when the first bus error

occurred.

0: Illegal address access not made

1: Illegal address access made

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