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H8/3003 Datasheet(PDF) 431 Page - Renesas Technology Corp |
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H8/3003 Datasheet(HTML) 431 Page - Renesas Technology Corp |
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431 / 715 page  Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock sources, obtained by prescaling the system clock (ø), for input to TCNT. Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 Description 0 0 0 ø/2 (Initial value) 1 ø/32 1 0 ø/64 1 ø/128 1 0 0 ø/256 1 ø/512 1 0 ø/2048 1 ø/4096 12.2.3 Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable and writable*1 register that indicates when a reset signal has been generated by watchdog timer overflow, and controls external output of the reset signal. Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by reset signals generated by watchdog timer overflow. Notes: 1. RSTCSR is write-protected by a password. For details see section 12.2.4, Notes on Register Access. 2. Only 0 can be written in bit 7, to clear the flag. Bit Initial value Read/Write 7 WRST 0 R/(W) 6 RSTOE 0 R/W 5 — 1 — 4 — 1 — 3 — 1 — 0 — 1 — 2 — 1 — 1 — 1 — * Watchdog timer reset Indicates that a reset signal has been generated Reserved bits Reset output enable Enables or disables external output of the reset signal 2 413 |
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