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H8/3003 Datasheet(PDF) 432 Page - Renesas Technology Corp |
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H8/3003 Datasheet(HTML) 432 Page - Renesas Technology Corp |
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432 / 715 page  Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3003 chip internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to initialize external system devices. Bit 7 WRST Description 0 [Clearing condition] Cleared to 0 by reset signal input at RES pin, or by writing 0 (Initial value) 1 [Setting condition] Set when TCNT overflow generates a reset signal during watchdog timer operation Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin of the reset signal generated if TCNT overflows during watchdog timer operation. Bit 6 RSTOE Description 0 Reset signal is not output externally (Initial value) 1 Reset signal is output externally Bits 5 to 0—Reserved: Read-only bits, always read as 1. 414 |
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