H8SLASH3003 datasheet(532/715 Pages) RENESAS

532 / 715 page

17.3 Sleep Mode

17.3.1 Transition to Sleep Mode

When the SSBY bit is cleared to 0 in the system control register (SYSCR), execution of the

SLEEP instruction causes a transition from the program execution state to sleep mode.

Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal

registers are retained. The DMA controller (DMAC), refresh controller, and on-chip supporting

modules do not halt in sleep mode.

17.3.2 Exit from Sleep Mode

Sleep mode is exited by an interrupt, or by input at the

RES or STBY pin.

Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt

exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting

module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by

an interrupt other than NMI if the interrupt is masked by IPR and the I and UI bits in CCR.

Exit by

RES Input: Low input at the RES pin exits from sleep mode to the reset state.

Exit by

STBY Input: Low input at the STBY pin exits from sleep mode to hardware standby

mode.

514

H8/3003 Datasheet(PDF) 532 Page - Renesas Technology Corp