H8SLASH3003 datasheet(589/715 Pages) RENESAS

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A.3 Number of States Required for Execution

The tables in this section can be used to calculate the number of states required for instruction

execution by the H8/300H CPU. Table A-3 indicates the number of instruction fetch, data

read/write, and other cycles occurring in each instruction. Table A-2 indicates the number of states

required per cycle according to the bus size. The number of states required for execution of an

instruction can be calculated from these two tables as follows:

Number of states = I

× S

I + J × SJ + K × SK + L × SL + M × SM + N × SN

Examples of Calculation of Number of States Required for Execution

Examples: Advanced mode, stack located in external address space, on-chip supporting modules

accessed with 8-bit bus width, external devices accessed in three states with one wait state and

16-bit bus width.

BSET #0, @FFFFC7:8

From table A-3, I = L = 2 and J = K = M = N = 0

From table A-2, SI = 4 and SL = 3

Number of states = 2

× 4 + 2 × 3 = 14

JSR @@30

From table A-3, I = J = K = 2 and L = M = N = 0

From table A-2, SI = SJ = SK = 4

Number of states = 2

× 4 + 2 × 4 + 2 × 4 = 24

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