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H8/3003 Datasheet(PDF) 102 Page - Renesas Technology Corp |
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H8/3003 Datasheet(HTML) 102 Page - Renesas Technology Corp |
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102 / 715 page ![]() 5.2.3 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ0 to IRQ7 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0—IRQ7 to IRQ0 Flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. Bits 7 to 0 IRQ7F to IRQ0F Description 0 [Clearing conditions] (Initial value) 0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1. IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out. IRQnSC = 1 and IRQn interrupt exception handling is carried out. 1 [Setting conditions] IRQnSC = 0 and IRQn input is low. IRQnSC = 1 and IRQn input changes from high to low. Note: n = 7 to 0 Bit Initial value Read/Write 7 IRQ7F 0 R/(W) These bits indicate IRQ to IRQ interrupt request status Note: Only 0 can be written, to clear flags. * * 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* 70 IRQ to IRQ flags 70 84 |
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