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H8/3003 Datasheet(PDF) 125 Page - Renesas Technology Corp |
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H8/3003 Datasheet(HTML) 125 Page - Renesas Technology Corp |
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125 / 715 page ![]() Bits 1 and 0—Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted in access to external three-state-access areas. Bit 1 Bit 0 WC1 WC0 Description 0 0 No wait states inserted by wait-state controller 1 1 state inserted 1 0 2 states inserted 1 3 states inserted (Initial value) 6.2.4 Wait State Control Enable Register (WCER) WCER is an 8-bit readable/writable register that enables or disables wait-state control of external three-state-access areas by the wait-state controller. WCER is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0—Wait-State Control Enable 7 to 0 (WCE7 to WCE0): These bits enable or disable wait-state control of external three-state-access areas. Bits 7 to 0 WCE7 to WCE0 Description 0 Wait-state control disabled (pin wait mode 0) 1 Wait-state control enabled (Initial value) Bit Initial value Read/Write 7 WCE7 1 R/W 6 WCE6 1 R/W 5 WCE5 1 R/W 4 WCE4 1 R/W 3 WCE3 1 R/W 0 WCE0 1 R/W 2 WCE2 1 R/W 1 WCE1 1 R/W Wait state controller enable 7 to 0 These bits enable or disable wait-state control 107 |
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