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H8/3003 Datasheet(PDF) 126 Page - Renesas Technology Corp |
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H8/3003 Datasheet(HTML) 126 Page - Renesas Technology Corp |
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126 / 715 page  6.2.5 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables or disables release of the bus to an external device. BRCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 1—Reserved: Read-only bits, always read as 1. Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external device. Bit 0 BRLE Description 0 The bus cannot be released to an external device; BREQ and BACK (Initial value) can be used as input/output pins 1 The bus can be released to an external device Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 0 BRLE 0 R/W 2 — 1 — 1 — 1 — Bus release enable Enables or disables release of the bus to an external device Reserved bits 108 |
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