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H8/3003 Datasheet(PDF) 159 Page - Renesas Technology Corp |
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H8/3003 Datasheet(HTML) 159 Page - Renesas Technology Corp |
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159 / 715 page ![]() 7.2.2 Refresh Timer Control/Status Register (RTMCSR) RTMCSR is an 8-bit readable/writable register that selects the clock source for RTCNT. It also enables or disables interrupt requests when the refresh controller is used as an interval timer. Bits 7 and 6 are initialized by a reset and in standby mode. Bits 5 to 3 are initialized by a reset and in hardware standby mode, but retain their previous values on transition to software standby mode. Bit 7—Compare Match Flag (CMF): This status flag indicates that the RTCNT and RTCOR values have matched. Bit 7 CMF Description 0 [Clearing condition] Cleared by reading CMF when CMF = 1, then writing 0 in CMF 1 [Setting condition] When RTCNT = RTCOR Bit Initial value Read/Write 7 CMF 0 R/(W) 6 CMIE 0 R/W 5 CKS2 0 R/W 4 CKS1 0 R/W 3 CKS0 0 R/W 0 — 1 — 2 — 1 — 1 — 1 — Compare match flag Status flag indicating that RTCNT has matched RTCOR Reserved bits Clock select 2 to 0 These bits select an internal clock source for input to RTCNT Note: Only 0 can be written, to clear the flag. * * Compare match interrupt enable Enables or disables the CMI interrupt requested by CMF 141 |
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