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H8/3003 Datasheet(PDF) 178 Page - Renesas Technology Corp

Part # H8/3003
Description  microcontroller (MCU)
PDF  715 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8/3003 Datasheet(HTML) 178 Page - Renesas Technology Corp

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7.3.3 Pseudo-Static RAM Refresh Control
Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is
determined as in a DRAM interface, by the settings of RTCOR and bits CKS2 to CKS0 in
RTMCSR. The numbers of states required for pseudo-static RAM read/write cycles and refresh
cycles are the same as for DRAM (see table 7-4). The state transitions are as shown in figure 7-3.
Pseudo-Static RAM Control Signals: Figure 7-15 shows the control signals for pseudo-static
RAM read, write, and refresh cycles.
Figure 7-15 Pseudo-Static RAM Control Signal Output Timing
ø
CS
RD
HWR
LWR
RFSH
AS
3
Read cycle
Write cycle *
Refresh cycle
Area 3 top address
Note:
16-bit access
*
Address
bus
160



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