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H8/3003 Datasheet(PDF) 179 Page - Renesas Technology Corp |
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H8/3003 Datasheet(HTML) 179 Page - Renesas Technology Corp |
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179 / 715 page ![]() Refresh Cycle Priority Order: When there are simultaneous bus requests, the priority order is: (High) External bus master > refresh controller > DMA controller > CPU (Low) For details see section 6.3.7, Bus Arbiter Operation. Wait State Insertion: When bit AST3 is set to 1 in ASTCR, the wait state controller (WSC) can insert wait states into bus cycles and refresh cycles. For details see section 6.3.5, Wait Modes. Self-Refresh Mode: Some pseudo-static RAM devices have a self-refresh function. After the SRFMD bit is set to 1 in RFSHCR, when a transition to software standby mode occurs, the H8/3003’s CS3 output goes high and its RFSH output goes low so that the pseudo-static RAM self-refresh function can be used. On exit from software standby mode, the RFSH output goes high. Table 7-8 shows the pin states in software standby mode. Figure 7-16 shows the signal output timing. Table 7-8 Pin States in Software Standby Mode (2) (PSRAME = 1, DRAME = 0) Software Standby Mode Signal SRFMD = 0 SRFMD = 1 (self-refresh mode) CS3 High High RD High-impedance High-impedance HWR High-impedance High-impedance LWR High-impedance High-impedance RFSF High Low 161 |
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