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PCIMX258CJM4A Datasheet(PDF) 57 Page - Freescale Semiconductor, Inc |
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PCIMX258CJM4A Datasheet(HTML) 57 Page - Freescale Semiconductor, Inc |
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57 / 144 page  i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3 Freescale Semiconductor 57 Figure 25. SDRAM Read Cycle Timing Diagram Table 42. DDR/SDR SDRAM Read Cycle Timing Parameters ID Parameter Symbol Min. Max. Unit SD1 SDRAM clock high-level width1 tCH 3.4 4.1 ns SD2 SDRAM clock low-level width1 tCL 3.4 4.1 ns SD3 SDRAM clock cycle time tCK 7.5 — ns SD4 CS, RAS, CAS, WE, DQM, CKE setup time tCMS 2.0 — ns SD5 CS, RAS, CAS, WE, DQM, CKE hold time tCMH 1.8 — ns SD6 Address setup time tAS 2.0 — ns SD7 Address hold time tAH 1.8 — ns SD8 SDRAM access time tAC — 6.47 ns SDCLK WE ADDR DQ DQM COL/BA Data CS CAS RAS Note: CKE is high during the read/write cycle. SD4 SD1 SD3 SD2 SD4 SD4 SD4 SD4 SD5 SD5 SD5 SD5 SD5 SD6 SD7 SD10 SD8 SD9 SDCLK ROW/BA |
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