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PCIMX258CJM4A Datasheet(PDF) 58 Page - Freescale Semiconductor, Inc |
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PCIMX258CJM4A Datasheet(HTML) 58 Page - Freescale Semiconductor, Inc |
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58 / 144 page  i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3 58 Freescale Semiconductor Figure 26. SDR SDRAM Write Cycle Timing Diagram SD9 Data out hold time2 tOH 1.2 — ns SD10 Active to read/write command period tRC 10 — clock 1 SD1 + SD2 does not exceed 7.5 ns for 133 MHz. 2 Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see Table 46 and Table 47. Table 42. DDR/SDR SDRAM Read Cycle Timing Parameters (continued) ID Parameter Symbol Min. Max. Unit CS CAS WE RAS ADDR DQ DQM BA ROW / BA COL/BA DATA SD4 SD4 SD4 SD4 SD5 SD5 SD5 SD5 SD7 SD6 SD12 SD13 SD14 SD11 SDCLK SD1 SD3 SD2 SDCLK |
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