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PCIMX258CJM4A Datasheet(PDF) 60 Page - Freescale Semiconductor, Inc |
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PCIMX258CJM4A Datasheet(HTML) 60 Page - Freescale Semiconductor, Inc |
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60 / 144 page  i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3 60 Freescale Semiconductor Figure 28. SDRAM Self-Refresh Cycle Timing Diagram NOTE The clock continues to run unless CKE is low. Then the clock is stopped in low state. Table 44. SDRAM Refresh Timing Parameters ID Parameter Symbol Min. Max. Unit SD1 SDRAM clock high-level width tCH 3.4 4.1 ns SD2 SDRAM clock low-level width tCL 3.4 4.1 ns SD3 SDRAM clock cycle time tCK 7.5 — ns SD6 Address setup time tAS 1.8 — ns SD7 Address hold time tAH 1.8 — ns SD10 Precharge cycle period1 1 SD10 and SD11 are determined by SDRAM controller register settings. tRP 1 4 clock SD11 Auto precharge command period1 tRC 2 20 clock SDCLK CS CAS RAS ADDR BA WE CKE Don’t care SD16 SD16 |
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