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PCIMX258CJM4A Datasheet(PDF) 68 Page - Freescale Semiconductor, Inc |
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PCIMX258CJM4A Datasheet(HTML) 68 Page - Freescale Semiconductor, Inc |
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68 / 144 page  i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3 68 Freescale Semiconductor Figure 36. Write Data Latch Cycle Timing Diagram Figure 37. Read Data Latch Cycle Timing Diagram Table 53. NFC Timing Parameters1 ID Parameter Symbol Timing T = NFC Clock Cycle Example Timing for NFC Clock ≈ 33 MHz T = 30 ns Unit Min. Max. Min. Max. NF1 NFCLE setup time tCLS T–1.0 ns — 29 — ns NF2 NFCLE hold time tCLH T–2.0 ns — 28 — ns NF3 NFCE setup time tCS 2T–5.0 ns — 55 — ns NF4 NFCE hold time tCH 7T–5.0 ns — 205 — ns NFCLE NFCE NFWE NFALE NFIO[15:0] Data to NF NF9 NF8 NF1 NF5 NF3 NF6 NF11 NF10 NF7 NFCLE NFCE NFRE NFRB NFIO[15:0] Data from NF NF13 NF15 NF14 NF17 NF12 NF16 |
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