PCIMX258CJM4A datasheet(66/144 Pages) FREESCALE

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i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

Freescale Semiconductor

Figure 33. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram

DQ Slew Rate

V/ns

2.0 188

188

167

146

125

————

————————

1.5 146

167

125

—

————————

1.0 63

125

–2

–7

–13

————————

0.9

—

–11

–14

–13

–18

–27

–29

–45

——————

0.8

————

–25

–31

–27

–30

–32

–44

–43

–62

–60

–86

————

0.7

—————

—

–45

–53

–50

–67

–61

–85

–78 –109 –108 –152

—

0.6

—————

———

–74

–96

–85 –114 –102 –138 –132 –181 –183 –246

0.5

—————

–128 –156 –145 –180 –175 –223 –226 –288

0.4

—————

—

–210 –243 –240 –286 –291 –351

1 All units in ‘ps’.

2 Test conditions are at capacitance=15pF for DDR PADS. Recommended drive strengths are medium for SDCLK and high for

address and controls.

3 SDRAM CLK and DQS related parameters are measured from the 50% point. That is, high is defined as 50% of the signal

value, and low is defined as 50% of the signal value. DDR SDRAM CLK parameters are measured at the crossing point of

SDCLK and SDCLK (inverted clock).

Table 52. DDR2 SDRAM Read Cycle Parameter Table1,2

1 Test conditions are at capacitance=15 pF for DDR PADS. Recommended drive strengths are medium for SDCLK and high for

address and controls.

Parameter

Symbol

DDR2-400

Unit

Min.

Max.

DDR24 DQS - DQ Skew (defines the Data valid window in read cycles related to DQS)

tDQSQ

—0.35

DDR25 DQS DQ in HOLD time from DQS3

tQH

2.925

—

DDR26 DQS output access time from SDCLK posedge

tDQSCK

–0.5

0.5

Table 51.

ΔtDS1, ΔtDH1 Derating Values for DDR2-400, DDR2-5331,2,3 (continued)

DQS Single-Ended Slew Rate

SDCLK

SDCLK_B

DQS (input)

DQ (input)

DATA

DDR26

DDR24

DDR25

PCIMX258CJM4A Datasheet(PDF) 66 Page - Freescale Semiconductor, Inc

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