MC9S08DN60F1CLF datasheet(211/356 Pages) FREESCALE

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Chapter 11 Inter-Integrated Circuit (S08IICV2)

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

211

Figure 11-12. Typical IIC Interrupt Routine

Clear

Master

Mode

Tx/Rx

Last Byte

Transmitted

RXAK=0

End of

Addr Cycle

(Master Rx)

Write Next

Byte to IICD

Switch to

Rx Mode

Dummy Read

from IICD

Generate

Stop Signal

Read Data

from IICD

and Store

Set TXACK =1

Generate

Stop Signal

2nd Last

Byte to Be Read

Last

Byte to Be Read

Arbitration

Lost

Clear ARBL

IAAS=1

SRW=1

TX/RX

Set TX

Mode

Write Data

to IICD

Set RX

Mode

Dummy Read

from IICD

ACK from

Receiver

Tx Next

Byte

Read Data

from IICD

and Store

Switch to

Rx Mode

Dummy Read

from IICD

RTI

(Write)

(Read)

IICIF

Address Transfer

Data Transfer

(MST = 0)

See Note 1

NOTES:

1. If general call is enabled, a check must be done to determine whether the received address was a general call address (0x00). If the received address was a

general call address, then the general call must be handled by user software.

2. When 10-bit addressing is used to address a slave, the slave sees an interrupt following the ﬁrst byte of the extended address. User software must ensure that for

this interrupt, the contents of IICD are ignored and not treated as a valid data transfer

See Note 2

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