MC9S08DN60F1CLF datasheet(217/356 Pages) FREESCALE

217 / 356 page

Chapter 12 Serial Peripheral Interface (S08SPIV3)

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

217

Figure 12-3. SPI Module Block Diagram

12.1.3

SPI Baud Rate Generation

As shown in Figure 12-4, the clock source for the SPI baud rate generator is the bus clock. The three

prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate

select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256

to get the internal SPI master mode bit-rate clock.

SPI SHIFT REGISTER

SHIFT

CLOCK

SHIFT

DIRECTION

Rx BUFFER

FULL

Tx BUFFER

EMPTY

SHIFT

OUT

SHIFT

ENABLE

SPI SYSTEM

CLOCK

LOGIC

CLOCK GENERATOR

BUS RATE

CLOCK

MASTER/SLAVE

MODE SELECT

MODE FAULT

DETECTION

MASTER CLOCK

SLAVE CLOCK

SPI

INTERRUPT

REQUEST

PIN CONTROL

MASTER/

SLAVE

MOSI

(MOMI)

MISO

(SISO)

SPSCK

MODF

SPE

LSBFE

MSTR

SPRF

SPTEF

SPTIE

SPIE

MODFEN

SSOE

SPC0

BIDIROE

SPIBR

Tx BUFFER (WRITE SPID)

Rx BUFFER (READ SPID)

MC9S08DN60F1CLF Datasheet(PDF) 217 Page - Freescale Semiconductor, Inc

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