MC9S08DN60F1CLF datasheet(185/356 Pages) FREESCALE

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Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

185

The maximum total conversion time is determined by the clock source chosen and the divide ratio selected.

The clock source is selectable by the ADICLK bits, and the divide ratio is speciﬁed by the ADIV bits. For

example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1

ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is:

NOTE

The ADCK frequency must be between fADCK minimum and fADCK

maximum to meet ADC speciﬁcations.

10.4.5

Automatic Compare Function

The compare function can be conﬁgured to check for an upper or lower limit. After the input is sampled

and converted, the result is added to the two’s complement of the compare value (ADCCVH and

ADCCVL). When comparing to an upper limit (ACFGT = 1), if the result is greater-than or equal-to the

compare value, COCO is set. When comparing to a lower limit (ACFGT = 0), if the result is less than the

compare value, COCO is set. The value generated by the addition of the conversion result and the two’s

complement of the compare value is transferred to ADCRH and ADCRL.

Upon completion of a conversion while the compare function is enabled, if the compare condition is not

true, COCO is not set and no data is transferred to the result registers. An ADC interrupt is generated upon

the setting of COCO if the ADC interrupt is enabled (AIEN = 1).

NOTE

The compare function can monitor the voltage on a channel while the MCU

is in wait or stop3 mode. The ADC interrupt wakes the MCU when the

compare condition is met.

10.4.6

MCU Wait Mode Operation

Wait mode is a lower power-consumption standby mode from which recovery is fast because the clock

sources remain active. If a conversion is in progress when the MCU enters wait mode, it continues until

completion. Conversions can be initiated while the MCU is in wait mode by means of the hardware trigger

or if continuous conversions are enabled.

The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in

wait mode. The use of ALTCLK as the conversion clock source in wait is dependent on the deﬁnition of

Subsequent continuous 10-bit or 12-bit;

fBUS > fADCK/11

40 ADCK cycles

Table 10-13. Total Conversion Time vs. Control Conditions

Conversion Type

ADICLK

ADLSMP

Max Total Conversion Time

23 ADCK Cyc

Conversion time =

8 MHz/1

Number of bus cycles = 3.5 ms x 8 MHz = 28 cycles

5 bus Cyc

8 MHz

= 3.5 ms

MC9S08DN60F1CLF Datasheet(PDF) 185 Page - Freescale Semiconductor, Inc

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