MC9S08DN60F1CLF datasheet(190/356 Pages) FREESCALE

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Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

MC9S08DN60 Series Data Sheet, Rev 3

190

Freescale Semiconductor

10.6.1.3

Analog Input Pins

The external analog inputs are typically shared with digital I/O pins on MCU devices. The pin I/O control

is disabled by setting the appropriate control bit in one of the pin control registers. Conversions can be

performed on inputs without the associated pin control register bit set. It is recommended that the pin

control register bit always be set when using a pin as an analog input. This avoids problems with contention

because the output buffer is in its high impedance state and the pullup is disabled. Also, the input buffer

draws DC current when its input is not at VDD or VSS. Setting the pin control register bits for all pins used

as analog inputs should be done to achieve lowest operating current.

Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise

or when the source impedance is high. Use of 0.01

μF capacitors with good high-frequency characteristics

is sufﬁcient. These capacitors are not necessary in all cases, but when used they must be placed as near as

possible to the package pins and be referenced to VSSA.

For proper conversion, the input voltage must fall between VREFH and VREFL. If the input is equal to or

exceeds VREFH, the converter circuit converts the signal to 0xFFF (full scale 12-bit representation), 0x3FF

(full scale 10-bit representation) or 0xFF (full scale 8-bit representation). If the input is equal to or less

than VREFL, the converter circuit converts it to 0x000. Input voltages between VREFH and VREFL are

straight-line linear conversions. There is a brief current associated with VREFL when the sampling

capacitor is charging. The input is sampled for 3.5 cycles of the ADCK source when ADLSMP is low, or

23.5 cycles when ADLSMP is high.

For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be

transitioning during conversions.

10.6.2

Sources of Error

Several sources of error exist for A/D conversions. These are discussed in the following sections.

10.6.2.1

Sampling Error

For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the

maximum input resistance of approximately 7k

Ω and input capacitance of approximately 5.5 pF, sampling

to within 1/4LSB (at 12-bit resolution) can be achieved within the minimum sample window (3.5 cycles @

8 MHz maximum ADCK frequency) provided the resistance of the external analog source (RAS) is kept

below 2 k

Ω.

Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the

sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time.

10.6.2.2

Pin Leakage Error

Leakage on the I/O pins can cause conversion error if the external analog source resistance (RAS) is high.

If this error cannot be tolerated by the application, keep RAS lower than VDDAD /(2

N*I

LEAK) for less than

1/4LSB leakage error (N = 8 in 8-bit, 10 in 10-bit or 12 in 12-bit mode).

MC9S08DN60F1CLF Datasheet(PDF) 190 Page - Freescale Semiconductor, Inc

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