MC9S08DN60F1CLF datasheet(191/356 Pages) FREESCALE

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Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

191

10.6.2.3

Noise-Induced Errors

System noise that occurs during the sample or conversion process can affect the accuracy of the

conversion. The ADC accuracy numbers are guaranteed as speciﬁed only if the following conditions are

met:

•

There is a 0.1

μF low-ESR capacitor from V

REFH to VREFL.

•

There is a 0.1

μF low-ESR capacitor from V

DDAD to VSSAD.

•

If inductive isolation is used from the primary supply, an additional 1

μF capacitor is placed from

VDDAD to VSSAD.

•VSSAD (and VREFL, if connected) is connected to VSS at a quiet point in the ground plane.

•

Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or

immediately after initiating (hardware or software triggered conversions) the ADC conversion.

— For software triggered conversions, immediately follow the write to ADCSC1 with a wait

instruction or stop instruction.

— For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces VDD

noise but increases effective conversion time due to stop recovery.

•

There is no I/O switching, input or output, on the MCU during the conversion.

There are some situations where external system activity causes radiated or conducted noise emissions or

excessive VDD noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in

wait or stop3 or I/O activity cannot be halted, these recommended actions may reduce the effect of noise

on the accuracy:

•

Place a 0.01

μF capacitor (C

AS) on the selected input channel to VREFL or VSSAD (this improves

noise issues, but affects the sample rate based on the external analog source resistance).

•

Average the result by converting the analog input many times in succession and dividing the sum

of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error.

•

Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and

averaging. Noise that is synchronous to ADCK cannot be averaged out.

10.6.2.4

Code Width and Quantization Error

The ADC quantizes the ideal straight-line transfer function into 4096 steps (in 12-bit mode). Each step

ideally has the same height (1 code) and width. The width is deﬁned as the delta between the transition

points to one code and the next. The ideal code width for an N bit converter (in this case N can be 8, 10 or

12), deﬁned as 1LSB, is:

1 lsb = (VREFH - VREFL) / 2

Eqn. 10-2

There is an inherent quantization error due to the digitization of the result. For 8-bit or 10-bit conversions

the code transitions when the voltage is at the midpoint between the points where the straight line transfer

function is exactly represented by the actual transfer function. Therefore, the quantization error will be

1/2 lsb in 8- or 10-bit mode. As a consequence, however, the code width of the ﬁrst (0x000) conversion is

only 1/2 lsb and the code width of the last (0xFF or 0x3FF) is 1.5 lsb.

MC9S08DN60F1CLF Datasheet(PDF) 191 Page - Freescale Semiconductor, Inc

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