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MPC5125 Datasheet(PDF) 32 Page - Freescale Semiconductor, Inc |
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MPC5125 Datasheet(HTML) 32 Page - Freescale Semiconductor, Inc |
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32 / 92 page ![]() PSC1_2 0x7D STD_PU ALT0 ALT1 ALT2 ALT3 PSC1_2 TPA2 GPT1[7] IRQ1 PSC1 GPT1 I/O I/O I VDD_IO — B14 PSC1_3 0x7E STD_PU ALT0 ALT1 ALT2 ALT3 PSC1_3 CKSTP_IN NFC_R/B2 GPIO19 PSC1 NFC GPIO1 I/O O I/O VDD_IO — D13 PSC1_4 0x7F STD_PU ALT0 ALT1 ALT2 ALT3 PSC1_4 CKSTP_OUT NFC_CE2 GPIO20 PSC1 MFC GPIO1 I/O O I/O VDD_IO — A15 J1850_TX 0x80 STD_PU_ST ALT0 ALT1 ALT2 ALT3 J1850_TX — NFC_CE3 I2C1_SCL J1850 — NFC I2C1 O — O I/O VDD_IO — B5 J1850_RX 0x81 STD_PU_ST ALT0 ALT1 ALT2 ALT3 J1850_RX — NFC_R/B3 I2C1_SDA J1850 — NFC I2C1 I — O I/O VDD_IO — C6 JTAG TCK — ALT0 ALT1 ALT2 ALT3 TCK — — — JTAG — — — I — — — VDD_IO 5. This pin contains an enabled internal Schmitt trigger. C16 TDI — ALT0 ALT1 ALT2 ALT3 TDI — — — JTAG — — — I — — — VDD_IO 3. This JTAG pin has an internal pullup P-FET, and cannot be configured. C15 TDO — ALT0 ALT1 ALT2 ALT3 TDO — — — JTAG — — — O — — — VDD_IO — B16 Table 2. MPC5125 Pin Multiplexing (continued) Pin Pad I/O Control Register1 and Offset2 Alternate Function3 Functions4 Peripheral5 I/O Direction Power Domain Notes Pin |
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