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MPC5125 Datasheet(PDF) 45 Page - Freescale Semiconductor, Inc |
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MPC5125 Datasheet(HTML) 45 Page - Freescale Semiconductor, Inc |
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45 / 92 page  Electrical and Thermal Characteristics MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 45 4.2.3 System PLL Electrical Characteristics 4.2.4 e300 Core PLL Electrical Characteristics The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage-controlled core PLL. Table 15. System PLL Specifications Characteristic Sym Min Typical Max Unit SpecID Sys PLL input clock frequency1 NOTES: 1 The SYS_XTAL frequency and PLL configuration bits must be chosen such that the resulting system frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. fsys_xtal 16 33.3 67 MHz O3.1 Sys PLL input clock jitter2 2 This represents total input jitter — short term and long term combined. Two different types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected. Systemic jitter is passed into and through the PLL to the internal clock circuitry. tjitter — — 10 ps O3.2 Sys PLL VCO frequency1 fVCOsys 400 — 800 MHz O3.3 Sys PLL VCO output jitter (Dj), peak to peak / cycle fVCOjitterDj — — 40 ps O3.4 Sys PLL VCO output jitter (Rj), RMS 1 sigma fVCOjitterRj — — 12 ps O3.5 Sys PLL relock time — after power up3 3 PLL-relock time is the maximum amount of time required for the PLL lock after a stable VDD and CORE_SYSCLK are reached during the power-on reset sequence. tlock1 — — 200 µs O3.6 Sys PLL relock time — when power was on4 4 PLL-relock time is the maximum amount of time required for the PLL lock after the PLL has been disabled and subsequently re-enabled during sleep modes. tlock2 — — 170 µs O3.7 Table 16. e300 PLL Specifications Characteristic Sym Min Typical Max Unit SpecID e300 frequency1, 2 NOTES: 1 The frequency and e300 PLL configuration bits must be chosen such that the resulting system frequencies, CPU (core) frequency, and e300 PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies in Table 17. 2 The following hard-coded relationship exists between fcore and fVCOcore: (fcore = fVCOcore). fcore 200 — 400 MHz O4.1 e300 PLL VCO frequency1 fVCOcore 400 — 800 MHz O4.3 e300 PLL input clock frequency fCSB_CLK 50 — 200 MHz O4.4 e300 PLL input clock cycle time tCSB_CLK 5 — 20 ns O4.5 e300 PLL relock time3 3 PLL-relock time is the maximum amount of time required for the PLL lock after a stable V DD and CORE_SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes. tlock — — 200 µs O4.6 |
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