MPC5125 datasheet(34/92 Pages) FREESCALE

34 / 92 page

Test/Debug

TEST

—

ALT0

ALT1

ALT2

ALT3

TEST

—

VDD_IO

2. This pin is an input only.

This pin cannot be configured.

4. This test pin must be tied to

VSS.

D14

NOTES:

1 Pins controlled by the STD_PU_ST register have a Schmitt trigger input; pins controlled by the STD_PU register do not. Pins controlled by the

IO_CONTROL_MEM register access their alternate function ALT3 by setting the IO_CONTROL_MEM[16BIT] bit. This setting applies to all pins controlled by

IO_CONTROL_MEM. Pins not controlled by these registers are indicated with a “—”.

2 Offset from IOCONTROL_BASE (default is 0xFF40_A000).

3 Except where noted in the Notes column, ALT0 is the primary (default) function for each pin after reset.

4 Alternate functions are chosen by setting the values of the STD_PU[FUNCMUX] bitfields inside the I/O Control module.

– STD_PU[FUNCMUX] = 00

→ ALT0 (default)

– STD_PU[FUNCMUX] = 01

→ ALT1

– STD_PU[FUNCMUX] = 10

→ ALT2

– STD_PU[FUNCMUX] = 11

→ ALT3

For selecting alternate functions, the STD_PU and STD_PU_ST registers function the same. When no function is available on a pin’s given ALTn function (value

of STD_PU[FUNCMUX] ), it is shown as “—”.

5 Module included on the MCU.

Table 2. MPC5125 Pin Multiplexing (continued)

Pad I/O

Control

Register1

and Offset2

Alternate

Function3

Functions4

Peripheral5

I/O

Direction

Power Domain

Notes

MPC5125 Datasheet(PDF) 34 Page - Freescale Semiconductor, Inc

MPC5125 Datasheet(HTML) 34 Page - Freescale Semiconductor, Inc

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